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Computing with Memory
Results: 472

#	Item
81	Finalization should not be based on reachability Hans-J. Boehm HP Labs (This benefited from discussions with Mike Spertus and others.) Add to Reading List Source URL: hboehm.info Language: English - Date: 2014-02-06 19:37:32 Computer programming Data types Method Object-oriented programming Automatic memory management Finalizer Weak reference Destructor Keepalive Computing Software engineering Memory management
82	MSPC 2014 ACM SIGPLAN Workshop on Memory Systems Performance & Correctness 13 June 2014, co-located with PLDI 2014 General Chair Jeremy Singer, University of Glasgow Add to Reading List Source URL: mspcworkshop.org Language: English - Date: 2014-06-15 12:05:37 Association for Computing Machinery Programming Language Design and Implementation Computer memory Multi-core processor SIGPLAN Embedded system Computing Computer architecture Computer science
83	Eliminating Cache-Based Timing Attacks with Instruction-Based Scheduling Deian Stefan1 , Pablo Buiras2 , Edward Yang1 , Amit Levy1 , David Terei1 , Alejandro Russo2 , and David Mazières 1 Add to Reading List Source URL: www.amitlevy.com Language: English - Date: 2013-09-13 15:42:52 Cache Computer memory Computer architecture Scheduling Thread Timing attack Computing Central processing unit CPU cache
84	THE SYSTEM The 8510/a GRAPHICS COMPUTER SYSTEM consists of the Model 8510 DATA PROCESSOR, with FIS/EIS (Hardware floating point option) a 56K Byte memory/ video controller unit and the Model 8532 Keyboard/ Display. This Add to Reading List Source URL: bitsavers.trailing-edge.com Language: English - Date: 2003-07-07 00:00:00 Computer hardware Graphics chips Television technology Video Display Controller Atari 8-bit family Graphics hardware Dick Smith Super-80 Computer TRS-80 Color Computer Home computers Classes of computers Computing
85	Transaction Processing With General-Purpose Servers How Solid Data File Caching Technology Delivers Real-Time Transaction and Messaging Performance May 2002 Add to Reading List Source URL: www.soliddata.com Language: English - Date: 2012-02-11 16:21:34 System software Cache Computer memory Relational database management systems CPU cache Computer data storage Oracle Database Solid-state drive File system Computing Software Database management systems
86	AntiLog V4.1 User Guide Supplement Development Issue 0.1 © Anticyclone Systems Limited, 28 Jan 2007 You have been supplied with an early development release of the V4.1 AntiLog embedded software as part of our continued Add to Reading List Source URL: www.zen30649.zen.co.uk Language: English - Date: 2008-04-22 18:29:18 Computing Data buffer Extensible Storage Engine Data Information Windows Vista Computer memory Arrays Circular buffer
87	June 11, 2012 Tohoku University Tohoku University Develops the World’s First 3-D Reconfigurable Spin Logic Chip with Spintronics Technology Add to Reading List Source URL: www.csis.tohoku.ac.jp Language: English - Date: 2012-06-07 22:56:49 Integrated circuit Computing Flash memory Electronic engineering Reconfigurable computing Field-programmable gate array Computer memory Computer hardware Non-volatile memory
88	Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:06 Computer hardware Computer memory Software pipelining AMD 10h Loop unwinding CPU cache Branch predication Explicitly parallel instruction computing Compiler optimizations Computing Computer architecture
89	USING THE ASDM72B LOW VOLTAGE SHARP FLASH ROM ADAPTER The LOW VOLTAGE SHARP FLASH ROM ADAPTER (PART#ASDM72B) allows the Andromeda Research EPROM+ programming system to support the 72 pin DIMM modules with attached LOW VO Add to Reading List Source URL: www.arlabs.com Language: English - Date: 2014-02-13 22:42:11 Digital media Computing EPROM Flash memory DIMM Microcontrollers Read-only memory Atmel AVR Computer memory Computer hardware Non-volatile memory
90	NM93CS06/CS46/CS56/CS66 (MICROWIRE TM Bus InterfaceBit Serial EEPROM with Data Protect and Sequential Read General Description The NM93CS06/CS46/CS56/CS66 devices are4096 bits, res Add to Reading List Source URL: www.pjrc.com Language: English - Date: 1999-04-24 16:01:28 Computer memory Central processing unit EEPROM Non-volatile memory Instruction set Assembly languages Instruction set architectures Computer architecture Computer hardware Computing

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